The present invention relates to stress analysis of integrated circuits, and more particularly, to fast techniques for identifying high-stress regions.
A typical integrated circuit device includes a number of interconnect layers alternating with dielectric layers, all superposing a silicon substrate. Many of the dielectric layers are also referred to as via layers, because they include holes, or vias, in specific locations to allow the formation of conductive material passing from one interconnect layer to another, or from one interconnect layer to a desired point on the substrate. The material in the via connects above to a conducting trace and below to either another conducting trace or to the substrate.
Material property mismatch between the interconnect material and the dielectric material often introduces thermal mismatch stress in the interconnect structures. Stresses can also arise from other sources such as intrinsic/grain growth, and residual stress can exist from previous process steps. High stress in localized regions, such as the region between two line ends or at vias, can lead to yield or field failures from dielectric cracking, interface de-bonding, or metal voiding. This problem has increased in significance with the adoption of low-k dielectric materials, which typically have lower mechanical strength than the more traditional dielectric materials, although it can arise with the traditional materials as well.
Because of the large amount of time and expense required to fabricate prototypes of integrated circuits for testing, it has become commonplace to extensively simulate integrated circuits at various stages in the process of converting the basic circuit design to the mask reticles or other representations ultimately used in the fabrication process. For mechanical stress distribution, simulations are usually performed based on the integrated circuit layout data. But since stress failure due to inter-layer material property mismatches is inherently a 3-dimensional problem, 3-dimensional stress analysis of volumetric (3-dimensional) regions of the device was typically required. Such analysis was typically performed using a 3-dimensional finite element analysis, which is exceedingly time consuming. It is prohibitive to analyze large layouts using this method. As a result, the design and technology community is not currently able to fully analyze large layouts for mechanical stress performance based on layout data.
It has now been recognized that because of the specific geometry and material composition of logic based interconnects, there is a strong correlation between high stress distributions on a 2-dimensional layout plane and that in the 3-dimensional interconnect structure defined by the 2-dimensional layout. In addition, it has been recognized that the analysis window for a 2-dimensional analysis can be quite small around the structures. Based on these insights and others a high performance stress analyzer can be developed which can allow a large design layout to be analyzed. Roughly described, the analyzer first scans layout layers with a 2-dimensional stress analyzer, to predict regions of high 2-dimensional stress. 3-dimensional structures corresponding to those 2-dimensional regions can then be further analyzed locally with a 3-dimensional stress simulator for more accurate volume stress distributions. The 2-dimensional analysis is much simpler and much quicker than a 3-dimensional analysis, and can greatly reduce the number and size of volumetric regions for 3-dimensional analysis. As a result, it is now practical to analyze the layout for an entire chip for high stress regions, and to do so much more quickly than was previously required to perform a 3-dimensional analysis on only a small part of the chip layout.
Although a 2-dimensional stress calculation of a planar region is known to approximate a full 3-dimensional stress calculation when either the third dimension (e.g. depth) is sufficiently small or there is little geometric variation in the third dimension, interconnect and via layers of modern-day devices typically are not so thin compared to their feature widths, and layout details vary from layer to layer. In addition, it can be seen from the above that stress-related integrated circuit reliability issues often arise from structures that extend deeply into the device, spanning multiple layers. Embodiments described herein do not necessarily approximate the 3-dimensional stress components from the 2-dimensional analysis; rather they use the 2-dimensional analysis to point to those 3-dimensional regions to be analyzed further for their 3-dimensional stress components.